1. Field
The disclosure relates to a method, system, and article of manufacture for synchronizing threads in simultaneous multi-threaded processor machines.
2. Background
A simultaneous multi-threaded (SMT) processor may execute a plurality of instructions from a plurality of threads every processor cycle. SMT process design may implement hardware multi-threading with superscalar processor technology to allow a plurality of threads to issue instructions each processor cycle. Unlike many other hardware multi-threaded architectures, in which only a single hardware context (i.e., thread) is active on any given cycle, SMT process design may allow all thread contexts to simultaneously compete for and share the resources of a SMT processor. SMT machines may provide higher instruction throughput and program speedups for a variety of applications in both multiprogrammed and parallel environments, in comparison to non-SMT machines.
A SMT machine may include a plurality of SMT processors. The plurality of SMT processors may be used to process instructions caused by user applications that run on the SMT machine, where the user applications may execute in an operating environment provided by an operating system. A hypervisor is a program that provides access to SMT processors, memory, and other resources to the operating system, such that, the operating system can allow user applications to execute. The hypervisor has a higher privilege than the operating system may act as an interface between the operating system and the plurality of SMT processors.